HDFS – Hardware Design Using F#, version 0.2

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On hubFS AndyMan has recently announced “Hardware Design F#”, HDFS, Version 0.2, based on a port of HDCaml, by Tom Hawkins, though rapidly acquiring a life of its own.  I blogged about version 0.1 a while back. Here are his release highlights:

 









  • Revised circuit design API.  Where possible standard operators are used and overloaded to allow integer and string arguments.
  • Improved simulator which should fix the bugs in V0.1 and adds a few extra optimisations.  Completely redesigned API makes it much nicer to work with.
  • Basic constant propogation optimisations applied automatically as circuits are built.
  • Fixed point data type. 

  • A few new library circuits.
  • HDCaml compatibility API.
  • The beginnings of a synthesizer for Xilinx FPGAs.  Although not complete, to me it’s quite remarkable what a few hundred lines of ML can achieve.  Main things still to do:

    •   Memory generation (distributed and block ram).
    •   Hard multiplier support.
    •   Fix buggy instantiation code.
    •   EDIF generator (trying to reverse engineer EDIF is about as much fun as pulling out your own teeth…).

  • Matlab Simulink model generator, kindly provided by John White.

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